SEL1=0, SEL0=0
Crossbar B Select Register 0
| SEL0 | Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) 0 (0): CMP0 Output 1 (1): CMP1 Output 2 (2): CMP2 Output 3 (3): CMP3 Output 4 (4): FTM0 all channels output compare ORed together 5 (5): FTM0 all channels counter init ORed together 6 (6): FTM3 all channels output compare ORed together 7 (7): FTM3 all channels counter init ORed together 8 (8): PWMA channel 0 trigger 0 9 (9): PWMA channel 1 trigger 0 10 (10): PWMA channel 2 trigger 0 11 (11): PWMA channel 3 trigger 0 12 (12): PDB0 channel 0 output trigger 13 (13): High Speed Analog-to-Digital Converter 0 conversion A complete 14 (14): XBAR0_IN2 input pin 15 (15): XBAR0_IN3 input pin 16 (16): FTM1 all channels output compare ORed together 17 (17): FTM1 all channels counter init ORed together 18 (18): DMA channel 0 done 19 (19): DMA channel 1 done 20 (20): XBAR0_IN10 input pin 21 (21): XBAR0_IN11 input pin 22 (22): DMA channel 6 done 23 (23): DMA channel 7 done 24 (24): PIT trigger 0 25 (25): PIT trigger 1 26 (26): PDB1 channel 0 output trigger 27 (27): High Speed Analog-to-Digital Converter 0 conversion B complete 28 (28): PWMB channel 0 trigger 0 or trigger 1 29 (29): PWMB channel 1 trigger 0 or trigger 1 30 (30): PWMB channel 2 trigger 0 or trigger 1 31 (31): PWMB channel 3 trigger 0 or trigger 1 32 (32): FTM2 all channels output compare ORed together 33 (33): FTM2 all channels counter init ORed together 34 (34): PDB0 channel 1 output trigger 35 (35): PDB1 channel 1 output trigger 36 (36): High Speed Analog-to-Digital Converter 1 conversion A complete 37 (37): High Speed Analog-to-Digital Converter 1 conversion B complete 38 (38): Analog-to-Digital Converter 0 conversion complete |
| SEL1 | Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) 0 (0): CMP0 Output 1 (1): CMP1 Output 2 (2): CMP2 Output 3 (3): CMP3 Output 4 (4): FTM0 all channels output compare ORed together 5 (5): FTM0 all channels counter init ORed together 6 (6): FTM3 all channels output compare ORed together 7 (7): FTM3 all channels counter init ORed together 8 (8): PWMA channel 0 trigger 0 9 (9): PWMA channel 1 trigger 0 10 (10): PWMA channel 2 trigger 0 11 (11): PWMA channel 3 trigger 0 12 (12): PDB0 channel 0 output trigger 13 (13): High Speed Analog-to-Digital Converter 0 conversion A complete 14 (14): XBAR0_IN2 input pin 15 (15): XBAR0_IN3 input pin 16 (16): FTM1 all channels output compare ORed together 17 (17): FTM1 all channels counter init ORed together 18 (18): DMA channel 0 done 19 (19): DMA channel 1 done 20 (20): XBAR0_IN10 input pin 21 (21): XBAR0_IN11 input pin 22 (22): DMA channel 6 done 23 (23): DMA channel 7 done 24 (24): PIT trigger 0 25 (25): PIT trigger 1 26 (26): PDB1 channel 0 output trigger 27 (27): High Speed Analog-to-Digital Converter 0 conversion B complete 28 (28): PWMB channel 0 trigger 0 or trigger 1 29 (29): PWMB channel 1 trigger 0 or trigger 1 30 (30): PWMB channel 2 trigger 0 or trigger 1 31 (31): PWMB channel 3 trigger 0 or trigger 1 32 (32): FTM2 all channels output compare ORed together 33 (33): FTM2 all channels counter init ORed together 34 (34): PDB0 channel 1 output trigger 35 (35): PDB1 channel 1 output trigger 36 (36): High Speed Analog-to-Digital Converter 1 conversion A complete 37 (37): High Speed Analog-to-Digital Converter 1 conversion B complete 38 (38): Analog-to-Digital Converter 0 conversion complete |